The present invention relates to a semiconductor device in which bumps conducted to pads are formed at arbitrary positions, and a method of manufacturing the semiconductor device.
A recent trend in semiconductor elements has been further toward high mounting density, high integration and high operating speed, and with such a trend, a technique has been required to mount the semiconductor elements on a circuit board at a high mounting density.
A method of mounting semiconductor elements on a circuit board has been known, wherein semiconductor elements are covered with a ceramic or plastic package for protection from an external environment, and are mounted on the circuit board using terminals protruded therefrom. In recent years, a BGA package has been emerged to further increase the high mounting density, and further, an examination has been actively made to put to practical use a flip chip mounting technique for forming bumps on a chip (semiconductor element) and connecting the chip on a circuit board through bumps in a face-down manner.
Methods of forming bumps by plating have been disclosed, for example in Japanese Patent Laid-open No. Hei 4-352429. Next, one example of the methods of forming bumps by plating will be described with reference to FIGS. 1a to 1d.
Referring first to FIG. 1a, a barrier metal layer 3 is formed on an Al pad 2 of a semiconductor element 1 by vapor deposition in such a manner as to cover the entire upper surfaces of the semiconductor element 1 and the A1 pad 2.
A plating resist layer 4 is formed on the entire surface of the barrier metal layer 3, and only a portion, directly over the A1 pad 2, of the resist layer 4 is opened as shown in FIG. 1b using the known lithography and etching techniques.
The surface, formed with the A1 pad 2, of the semiconductor element 1 is dipped in an electrolytic solution, followed by current application, with a result that a mushroom-shaped solder bump 5 is formed at a position directly over the A1 pad 2 as shown in FIG. 1c.
The resist layer 4 and a unnecessary portion of the barrier metal layer 3 are removed by acid using the solder bump 5 as a mask. The solder bump 5 is then applied with flux, and fused by heat-treatment, to form a spherical bump 5a shown in FIG. 1d.
As is well known, the flip chip mounting has the following disadvantage. A semiconductor element is generally different in linear expansion coefficient from a circuit board, and accordingly a solder bump is susceptible to stress concentration due to heat generated by operation of the semiconductor device. As a result, the solder bump is liable to be cracked, and finally it comes to an electrically open state, that is, it is disconnected.
It is well-known that a strain due to such thermal stress is based on a Coffin-Mason equation described, for example in a handbook titled "High Reliability Micro-soldering Technique" (pp. 275) published by Industrial Research Institute. Various measures have been made, on the basis of such a knowledge, for prolonging the service life of bumps thereby keeping a conducting state between a semiconductor element and a circuit board through the bumps. For example, it is known that the increased height of bumps is effective to prolong the service life of the bump and hence to keep a conducting connection between a semiconductor element and a circuit board through the bumps.
However, in semiconductor elements required for high density and high integration used in an ASIC (Application Specific Integrated Circuit) or the like, an interval between A1 pads is narrowed because of a large number of output terminals. On the other hand, in the above-described plating method, a height of a bump 5 (5a) is limited by an interval between electrodes, that is, by an interval between A1 pads 2, 2. Specifically, in the case of forming a spherical bump 5a having a height more than the above limitation, mushroom-shaped bumps 5 are formed in a state being continuous to each other, which results in an electric short-circuit between electrodes (A1 pads 2,2), thus forming the bump 5a with a difficulty. For example, assuming that an interval between the A1 pads 2, 2 is 150 .mu.m and a practical thickness of a resist is 40 .mu.m, a height of the bump 5a is limited to about 70 .mu.m.
The prior art plating method, therefore, fails to form bumps on a semiconductor element on which A1 pads are arranged at narrow intervals.
The above-described vapor deposition method is also inconvenient in that upon vapor deposition for forming bumps, a metal mask is heated by vapor deposition and is thereby warped, making accuracy of a bump forming position unsatisfactory. The vapor deposition method is, therefore, undesirable for forming bumps arranged at narrow pitches like the above-described plating method.
A method of relaxing a thermal stress due to differences in linear expansion coefficients has been known, wherein bumps are arranged in a staggered manner for dispersing stress concentration applied to bumps [Soga et al.: Journal of Japanese Institute of Electronic Information Communication vol. J70-C, No. 12 (December, 1987), pp. 1575-1582]. In this case, however, for a given number of output terminals, an layout area of the semiconductor element having A1 pads that are arranged in a staggered manner must be made larger than that of a semiconductor element having A1 pads arranged in rows and columns at nearly equal intervals. This is undesirable in terms of cost and mounting density.
The prior art flip chip mounting technique thus fails to sufficiently obtain high reliability.
An interval between electrode terminals in a circuit board mounting semiconductor elements is also limited to about 150 .mu.m in terms of processing accuracy, and from this viewpoint, an interval between bumps cannot be also narrowed by the prior art flip chip mounting technique.
On the other hand, at present, an interval between A1 pads in a semiconductor element is fine to less than 100 .mu.m, and a technique is thus required to narrow the an interval between bumps up to a degree corresponding to the narrow interval between A1 pads and to make full use of the effect of high mounting density by the flip chip mounting. However, under the existing circumstances, such requirement cannot be satisfied from the above-described reasons.
Finally, since at present an interval between electrode terminals in a circuit board is made narrower up to a to match the high mounting density of semiconductor elements, the semiconductor elements, when mounted on the circuit board, must be positioned relative thereto at a high accuracy. This requires a high precision equipment for satisfying the above accurate positioning, resulting in the increased cost.